Method of anodizing silicon substrate and method of producing acceleration sensor

ABSTRACT

A method for anodizing silicon substrate includes forming an n-type silicon embedded layer ( 21 ) made of n-type silicon on a predetermined area of a first surface of the p-type single crystal silicon substrate ( 2 ). N-type silicon layers ( 4, 6 ) are formed on the upper surface of the p-type single crystal silicon substrate ( 2 ) and on the n-type silicon embedded layer ( 21 ). Silicon diffusion layers ( 5, 7 ) containing high-concentration p-type impurities are formed on predetermined areas of the n-type silicon layers ( 4, 6 ) to contact the n-type silicon embedded layer ( 21 ). An electrode layer ( 13 ) is formed on the lower surface of the p-type silicon substrate ( 2 ). The anode of a DC power source ( 15 ) is connected to the electrode layer ( 13 ), and the cathode is connected to a counter electrode ( 23 ), which is opposed to the p-type silicon substrate ( 2 ). A current is intensively applied to an area corresponding to an opening ( 21   a ) of the n-type silicon layer ( 4 ) in a direction from the lower surface to the upper surface of the p-type single crystal silicon substrate ( 2 ), which makes the area porous.

BACKGROUND OF THE INVENTION

The present invention relates to a method for anodizing siliconsubstrates and a method for manufacturing acceleration sensors using theanodization method.

In recent years, acceleration sensors have been used in controllingdevices such as ABS (antilock brake system), airbag systems, andsuspension control systems. A surface-type acceleration sensor is knownas a kind of acceleration sensor. The surface-type acceleration sensorincludes a silicon substrate, a displaceable mass portion formed on theupper surface of the substrate, and a deformation gauge formed on thesurface of the mass portion. In recent years, anodization technologieshave been used to form the mass portion. With reference to FIGS. 9-11, amethod for manufacturing a conventional surface-type acceleration sensor41 using anodization will now be described.

FIG. 9 shows a p-type single crystal silicon substrate 42, which isanodized. On a predetermined area of the upper surface of the p-typesingle crystal silicon substrate 42, a p⁺ silicon embedded layer 43 isformed. A first epitaxial growth layer 44, which is made of n-typesilicon, is laminated on the substrate 42. p⁺ silicon diffusion layers45 are embedded in predetermined areas of the first epitaxial growthlayer 44. A second epitaxial growth layer 46, which is made of n-typesilicon, is laminated on the first epitaxial growth layer 44. On apredetermined area of the second epitaxial growth layer 46, p⁺ silicondiffusion layers 47 are formed and are exposed to the exterior. On thesecond epitaxial growth layer 46, oxide film 48, wiring patterns 49,passivation film 50, and metal protection film 51 are formed. Adeformation gauge (not shown) is also formed in the second epitaxialgrowth layer 46. An oxide film 52 and an electrode layer 53 arelaminated in that order on the bottom surface of the substrate 42. Theelectrode layer 53 is electrically connected to the substrate 42 througha connection opening 54.

To perform anodization, the anode of a DC power supply 55 is connectedto the electrode layer 53, and the cathode is connected to a counterelectrode (not shown). In this state, the substrate 42 and the counterelectrode are immersed in a hydrofluoric acid solution. Then, a directcurrent I flows from the lower side of the substrate 42 to the upperside, which selectively becomes porous. During anodization, mainly theembedded layer 43, the diffusion layer 45, and the diffusion layer 47are changed into porous silicon layer 56 (see FIG. 10).

Then, the porous silicon layer 56 is selectively dissolved and removedby etching using alkaline etchant, which makes the substrate 42, whichincludes the layers 44, 46, hollow. As a result, mass portions 57 areformed on the epitaxial growth layers 44, 46, which form theacceleration sensor 41 as shown in FIG. 11.

However, in the conventional method, the direct current is applied to anarea outside the area designated for anodization. This slows theanodization. Accordingly, a more efficient anodization method has beenrequested.

Also, in the conventional method, the range that becomes porous may bewider than the designated area. This increases the amount of the porouspart that is removed by the etching and reduces the size of the massportions 57. In this way, the amount of wasteful removal increases andit is difficult to form a large mass portion 57. Therefore, it isdifficult to produce a highly sensitive surface-type acceleration sensorusing the anodization method.

Further, in the conventional method, holes may be formed in the sidesurfaces when the porous part is expanded to the periphery of thesubstrate 42. To avoid this, the size of substrate must be increased,which prevents making the acceleration sensors compact.

SUMMARY OF THE INVENTION

To solve the above problems, an objective of the present invention is toprovide an anodization method for silicon substrates that efficientlymakes a designated area porous.

Another objective of the present invention is to provide a method formanufacturing compact and highly sensitive surface-type accelerationsensors.

To achieve the above objectives, the present invention provides a methodfor anodizing a silicon substrate comprising: providing a p-type singlecrystal silicon substrate; forming an n-type silicon embedded layer madeof n-type silicon on a predetermined area of a first surface of thep-type single crystal silicon layer, wherein an opening for permitting acurrent to flow is formed in the center of the n-type silicon embeddedlayer; forming an n-type silicon layer on the first surface of thep-type single crystal silicon substrate and on the n-type siliconembedded layer; forming a silicon diffusion layer containing ahigh-concentration p-type impurity on a predetermined area of the n-typesilicon layer, wherein the silicon diffusion layer contacts at least then-type silicon embedded layer in the vicinity of the interface betweenthe p-type single crystal silicon substrate and the n-type siliconembedded layer; forming an electrode layer on a second surface, which ison the opposite side of the p-type silicon substrate from the firstsurface; connecting the anode of a DC power source to the electrodelayer and connecting the cathode to a counter electrode, which isopposed to the p-type silicon substrate; and concentrating a currentflow to an area corresponding to the opening of the n-type silicon layerin a direction from the second surface of the p-type single crystalsilicon substrate toward the first surface, and advancing porosityformation in the area from the first surface toward the second surface.

In the present invention, a direct current is intensely applied to anarea corresponding to an opening of the p-type single crystal siliconsubstrate during the anodization. Accordingly, the current isefficiently applied to the designated area, which increases theanodization speed and prevents the area outside the designated area frombecoming porous.

The present invention also provides a method for manufacturing asurface-type acceleration sensor having a displaceable mass portionformed on an upper surface of a silicon substrate and a deformationgauge formed on the upper surface of the mass portion, the methodcomprising: providing a p-type single crystal silicon substrate; formingan n-type silicon embedded layer made of n-type silicon on apredetermined area of a first surface of the p-type single crystalsilicon layer, wherein an opening for permitting a current to flow isformed in the center of the n-type silicon embedded layer; forming ann-type silicon layer on the first surface of the p-type single crystalsilicon substrate and on the n-type silicon embedded layer; forming asilicon diffusion layer containing a high-concentration p-type impurityon a predetermined area of the n-type silicon layer, wherein the silicondiffusion layer contacts at least the n-type silicon embedded layer inthe vicinity of the interface between the p-type single crystal siliconsubstrate and the n-type silicon embedded layer; forming the deformationgauge on the n-type silicon layer; forming a wiring over the n-typesilicon layer; forming an electrode layer on a second surface, which ison the opposite side of the p-type silicon substrate from the firstsurface; connecting the anode of a DC power source to the electrodelayer and connecting the cathode to a counter electrode, which isopposed to the p-type silicon substrate; concentrating a current flow toan area corresponding to the opening of the n-type silicon layer in adirection from the second surface of the p-type single crystal siliconsubstrate toward the first surface, and changing the area into a poroussilicon layer from the first surface toward the second surface; andforming the mass portion by dissolving and removing the porous siliconlayer using alkali etching.

A semiconductor device preferable for anodization for making siliconporous comprises: a p-type single crystal silicon substrate; an n-typesilicon embedded layer, which is made of n-type silicon and is formed ona predetermined area of a first surface of the p-type single crystalsilicon substrate; an opening, which is located in the center of then-type silicon embedded layer to permit a flow of current; an n-typesilicon layer, which is formed on the first surface of the p-type singlecrystal silicon substrate and on the n-type silicon embedded layer; asilicon diffusion layer, which is formed in a predetermined area of then-type silicon layer in the vicinity of the interface between the p-typesingle crystal silicon substrate and the n-type silicon layer to contactat least the n-type silicon embedded layer; and a high-concentrationp-type impurity, which is contained in the silicon diffusion layer; andan electrode layer, which is formed on a second surface that is locatedon the opposite side of the p-type silicon substrate from the firstsurface.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic cross-sectional view of a silicon substrate, whichis anodized according to one embodiment of the present embodiment.

FIG. 2 is a schematic view of the silicon substrate of FIG. 1, which isconnected to a power supply so it can be anodized.

FIG. 3 is a schematic cross-sectional view of the silicon substrate inan early anodization stage.

FIG. 4 is a schematic cross-sectional view of the silicon substrate inthe middle anodization stage.

FIG. 5 is a schematic cross-sectional view of the silicon substrate thathas become porous through the anodization.

FIG. 6 is a schematic cross-sectional view of an acceleration sensor,which has been formed through alkaline etching.

FIG. 7 is a partial enlarged cross-sectional view of the siliconsubstrate during the anodization.

FIG. 8 is a schematic cross-sectional view of a silicon substrateshowing another example of the anodization method.

FIG. 9 is a schematic cross-sectional view of a silicon substrate, whichis anodized according to a conventional anodization method.

FIG. 10 is a schematic cross-sectional view of the silicon substrate ofFIG. 9, which has become porous through the anodization.

FIG. 11 is a schematic cross-sectional view of a completed accelerationsensor, which has been formed through alkaline etching.

BEST MODE FOR CARRYING OUT THE INVENTION

A method for manufacturing a surface-type acceleration sensor 1according to one embodiment of the present invention will now bedescribed with reference to FIGS. 1-7. First, the structure of asemiconductor element, which includes a p-type single crystal siliconsubstrate 2 and is anodized, will be described with reference to FIG. 1.

As shown in FIG. 1, the p-type single crystal silicon substrate 2 is arectangular parallelepiped and has an orientation flat (110). Thethickness of the substrate 2 is 500 μm-600 μm. Instead of the substrate2 having the orientation flat (110), a substrate having otherorientation flats, for example, (111), (100), may be used. When asubstrate having an orientation flat (100) is used, a more sensitiveacceleration sensor is produced. A first epitaxial growth layer 4, whichis made of n-type single crystal silicon, is laminated on the entiresubstrate 2. p⁺ silicon diffusion layers 5 are embedded in predeterminedareas of the first epitaxial growth layer 4. In the present embodiment,the p⁺ silicon diffusion layers do not contact the substrate 2. A secondepitaxial growth layer 6, which is made of n-type single crystalsilicon, is laminated on the first epitaxial growth layer 4. p⁺ silicondiffusion layers 7 are formed in predetermined areas of the secondepitaxial growth layer 6. The p⁺ silicon diffusion layers 7 are locatedto correspond to the positions of the p⁺ silicon diffusion layers 5 andcontact the layers 5. A plurality of diffusion-type deformation gauges28 (see FIG. 6) are formed on the upper surface of the second epitaxialgrowth layer 6. The deformation gauges 28 are located at the parts ofthe second epitaxial growth layer that will form beams 29 (imaginarilyshown in FIG. 6). Instead of the diffusion-type deformation gauges 28,thin-film deformation gauges, which are made of, for example, chromium(Cr) or polycrystal silicon, may be used.

As shown in FIG. 1, thin silicon oxide film (SiO₂ film) 8, which servesas an inter-layer insulation layer, is formed on the upper surface ofthe second epitaxial growth layer 6. Wiring patterns 9 and bonding pads(not shown), which are preferably made of aluminum using a physical filmformation method, such as sputtering and vacuum evaporation, are formedon the oxide film 8. The wiring patterns 9 and the bonding pads may bemade of other metals such as gold (Au). Contact holes (not shown) forconnecting layers are formed in predetermined parts of the oxide film 8corresponding to the deformation gauges 28. The wiring patterns 9 areelectrically connected to the deformation gauges 28 through the contactholes.

The wiring patterns 9 are electrically connected to the bonding pads,respectively. Conductive layers such as the wiring patterns 9 and theoxide film 8 are entirely covered with a passivation film (SiN film) 10to insulate the surface. Further, the passivation film 10 is entirelycovered with a metal protection film 11. The passivation film 10 and themetal protection film 11 are formed by the above physical film formationmethod. The passivation film 10 and the metal protection film 11 includeopenings 10 a, 11 a respectively. The p⁺ silicon diffusion layer 7 isexposed to the exterior through the opening 11 a.

Further, an n-type silicon embedded layer 21, which is made of n-typesilicon, is formed near the interface between the substrate 2 and thefirst epitaxial growth layer 4. The n-type silicon has fewer holes thatcontribute to anodization than the p-type silicon. The embedded layer 21is formed by injecting and diffusing impurities, and part of the layer21 is located in the first epitaxial growth layer 4 due to expansion.Therefore, the embedded layer 21 partly contacts the bottom of thesilicon diffusion layer 5. In FIG. 7, the contact between the layers 5,21 is shown by P1. The embedded layer 21 includes an opening 21 a forthe intensive flow of direct current in a designated area of thesubstrate 2. The opening 21 a is located to correspond to an areasurrounded by the p⁺ silicon diffusion layer 7 and the p⁺ silicondiffusion layer 5.

On the other hand, an oxide film 12, which serves as an insulationlayer, is entirely formed on the lower surface of the substrate 2. Anelectrode layer 13, which is preferably made of titanium (Ti) film or Crfilm, is formed on the oxide film 12. The electrode layer 13 iselectrically connected to the substrate 2 through a connection opening14. The connection opening 14 is located to correspond to the opening 21a of the embedded layer 21. The opening area of the connection opening14 is smaller than that of the opening 21 a. On the lower surface of thesubstrate 2 corresponding to the opening 14, a p⁺ silicon diffusionlayer 22 is formed to be electrically connected to the opening 14. Thep⁺ silicon diffusion layer 22 is preferably formed on an area as smallas the opening 21 a. The diffusion layer 22 is a high-concentrationimpurity diffusion layer, which includes more holes that contribute toanodization than the p-type silicon and helps a direct current to flowduring anodization.

A method for manufacturing the acceleration sensor 1 will now bedescribed with reference to FIGS. 2-6.

The substrate 2 in the state of FIG. 1 is formed prior to anodization.The substrate 2 is a rectangular parallelepiped and has an orientationflat (110). A mask (not shown) is formed on the upper surface of thesubstrate 2. Then, n-type impurities, such as phosphorous, are injectedand thermally diffused in the substrate 2. This forms the n-type siliconembedded layer 21 on the substrate 2. The opening 21 a is located at thecenter of the substrate 2 to correspond to the mass portion 17 (see FIG.6), which is formed later.

Then, the first epitaxial growth layer 4, which is made of n-type singlecrystal silicon, is formed by gas phase growth on the entire uppersurface of the substrate 2, including the embedded layer 21. As aresult, the embedded layer 21 is embedded in the first epitaxial growthlayer 4. Then, the mask (not shown) is formed on the first epitaxialgrowth layer 4. An opening is formed on a predetermined area of the maskby photoetching. p-type impurities, such as boron, are injected in thefirst epitaxial growth layer 4 through the opening preferably by the ionimplantation and are thermally diffused. This forms the p⁺ silicondiffusion layer 5 on the first epitaxial growth layer 4. The p³⁰ silicondiffusion layer 5 contacts the embedded layer 21, but does not reach theupper surface of the substrate 2. A certain gap G1 is secured betweenthe upper surface of the substrate 2 and the lower part of the p⁺silicon diffusion layer 5.

Then, the second epitaxial growth layer 6, which is made of n-typesingle crystal silicon, is formed by gas phase growth on the uppersurface of the first epitaxial growth layer 4. As a result, the p⁺silicon diffusion layer 5 is embedded in the second epitaxial growthlayer 6. Then, a mask (not shown) is formed on the second epitaxialgrowth layer 6, and an opening is formed on a predetermined area of themask by photoetching. The p⁺ silicon diffusion layer 7, which reachesthe p⁺ silicon diffusion layer 5, is formed in the second epitaxialgrowth layer 6 by the injection and thermal diffusion of the p-typeimpurities. The p⁺ silicon diffusion layers 5, 7 are located tocorrespond to the sides of a mass portion 17 (FIG. 6,) which is formedlater.

Then, a mask (not shown) is arranged on the upper surface of the secondepitaxial growth layer 6, and the p-type impurities are injected andthermally diffused through the mask. This forms the diffusiondeformation gauges 28 at the part of the mass portion 17 that is easilydisplaced. Then, the substrate 2 is heated in oxygen or air after theformation of the deformation gauges, which forms the oxide films 1, 12on the upper and lower surfaces of the substrate 2. Then, a contact hole(not shown) is formed at a predetermined part of the upper oxide film 8by photoetching.

Then, after sputtering or vacuum evaporation using Al (aluminum), thewiring patterns 9 and the bonding pads (not shown) are formed on theupper surface of the oxide film 8 by photolithography. Further, thepassivation film 10 having the opening 10 a is formed preferably usingCVD (chemical vapor deposition), by depositing SiN or Si³N⁴. After theformation of the passivation film, sputtering or vacuum evaporationpreferably using a hydrofluoric-acid-resistant metal such as W(tungsten) or Mo (molybdenum) and photolithography are performed, whichforms the metal protection film 11 with the opening 11 a on thepassivation film 10. Then, the oxide film 8 in the openings 10 a, 11 ais removed to expose the upper surface of the p⁺ silicon diffusion layer7.

The p-type impurities are injected and thermally diffused in the lowersurface of the substrate 2 with a mask (not shown) arranged under theoxide film 12. This forms the p⁺ silicon diffusion layer 22 on the lowersurface of the substrate 2 to correspond to the opening 14. Then,sputtering or vacuum evaporation, preferably using Ti, Cr is performed,which forms the electrode layer 13 on the entire surface of the oxidefilm 12. The electrode layer 13 is connected to the p⁺ silicon diffusionlayer 22 through the opening 14. The formation of the layers 13, 22 maybe performed either before or after the formation of the passivationfilm 10. The electrode layer 13 may be simultaneously formed using thesame metal as the metal protection film 11 when the protection film 11is physically formed.

The anodization of the substrate 2 will now be described. As shown inFIG. 2, an anodization tank 25 is filled with high-concentrationhydrofluoric acid solution 24, which serves as an acid solution foranodization. A counter electrode 23, which is preferably made ofplatinum, is immersed in the hydrofluoric acid solution 24 and faces theupper surface of the substrate 2. The electrode layer 13 is electricallyconnected to the anode of a DC power source 15, and the counterelectrode 23 is electrically connected to the cathode of the DC powersource 15. Accordingly, a direct current flows from the lower surface tothe upper surface of the substrate 2. The flow of the current is shownby the lines I in FIGS. 3, 4. The electrons flow opposite to the flow ofthe current, and the formation of a porous portion is performed alongthe flow of the current by the supply of electrons to the hole.

As shown in FIG. 3, the p⁺ silicon diffusion layer 7 on the uppermostsurface side first turns porous in the early stage of anodization, andthen, the p⁺ silicon diffusion layer 5 below turns porous. At this time,a current flows through the n-type silicon embedded layer 21 having asmall specific resistance (depletion layer at the pn connection isnarrow), rather than flow beyond the gap G1. Therefore, after the p⁺silicon diffusion layer 7 becomes porous, the n-type silicon embeddedlayer 21 becomes porous. This is because the injection of electrons inthe holes of the embedded layer 21 is dominant.

The porosity formation is schematically shown by FIG. 7. As shown inFIG. 7, the porosity formation advances isotropically from the contactpoint p1. When the porosity formation reaches the substrate 2, currentflows through the thin gap G1 of the epitaxial growth layer 4 (see FIG.4). This is because the p-type silicon has more holes than the n-typesilicon, and injection of electrons in the holes of the substrate 2becomes more dominant than in the holes of the embedded layer 21.Therefore, at this time, the porosity formation in the n-type siliconembedded layer 21 stops.

Also, electrons converge in the center of the substrate 2 and flowtoward the lower side. Accordingly, porosity is formed around theopening 21 a along the flow of the electrons.

When the above anodization is completed, all of the p⁺ diffusion layers5, 7, the vicinity of the opening 21 a in the substrate 2, and thevicinity of the contact point P1 of the embedded layer 21 are changed toa porous silicon layer 16.

After the anodization process, the metal protection film 11 isseparated. Then, etching is performed using alkaline etchant such asTHAM (tetrametyl ammonium hydroxide). An alkaline etchant, such as KOH,hydrazine, EPW (ethylenediamine-pyrocatechol-water) may be used. As aresult, as shown in FIG. 6, the porous silicon layer 16 is dissolved andremoved by anisotropic etching. The porous silicon layer 16 is moreeasily dissolved by alkali than a compact silicon layer, whichfacilitates the formation of a cavity 18. A mass portion 17, which ismainly made of the epitaxial growth layers 4, 6, is formed in the cavity18, and the acceleration sensor 1 is completed. The mass portion 17 isdisplaced when acceleration is applied. The acceleration sensor may be acantilever-type or a both-ends-fixed type.

The advantages of the present invention will now be described.

In the anodization method of the present invention, the n-type siliconembedded layer 21 is formed in advance near the interface between thesubstrate 2 and the first epitaxial growth layer 4 to partially contactthe p⁺ silicon diffusion layer 5. The n-type silicon has fewer holesthan the p-type silicon. The opening 21 a is formed in advance in apredetermined area of the n-type silicon embedded layer 21. Therefore, adirect current concentrates on the area corresponding to the opening 21a of the substrate 2. Accordingly, since the current effectively flowsin a predetermined area, the anodization speed is increased and only thedesignated area efficiently turns porous. Also, since the current isconcentrated on the designated area, the expansion of porosity formationon the undesignated peripheral area of the substrate 2 is prevented.Accordingly, holes are prevented from opening in the side wall of thesubstrate and there is no need to increase the size of the substrate 2.

In the anodization method of the present embodiment, the electrode film13 is electrically connected to the substrate 2 through the opening 14on the lower surface of the substrate 2, and the opening 14 is locatedto correspond to the opening 21 a. This causes the DC current to beconcentrated on the area corresponding to the opening 21 a (see FIGS. 3,4). Therefore, expansion of current to the periphery of the substrate 2is prevented, and only the designated area is efficiently turned porous.This contributes to selective porosity formation and improvingefficiency.

In the anodization method of the present embodiment, the p⁺ silicondiffusion layer 22 is formed in advance on the part corresponding to theopening 14 in the lower surface of the substrate 2. During theanodization, the direct current is given priority to flow to the p⁺silicon diffusion layer 22 and concentrates on the opening 14.

In the present embodiment, the acceleration sensor 1 is manufacturedusing the above efficient anodization method. Therefore, the area thatis dissolved and removed by alkali etching decreases and the formationof a large mass portion 17 is relatively easy regardless of the smallsize of the substrate 2. Therefore, a compact and highly sensitivesurface-type acceleration sensor 1 is efficiently manufactured. Thefollowing are reasons for the mass portion 17 being larger than in theprior art. In the prior art shown in FIG. 9, the p⁺ silicon embeddedlayer 43 is formed under the part on which the bottom surface of themass portion 17 is formed. However, the embedded layer 43 expands towardthe first epitaxial growth layer 44, which causes the porosity formationarea to expand upward. On the other hand, in the present embodiment, thep⁺ silicon embedded layer is not formed on the concerned part, and theabove problem is prevented and the first epitaxial growth layer 4 isprevented from becoming thin. The thicker the first epitaxial growthlayer 4, the larger the mass portion 17.

The method for manufacturing the acceleration sensor 1 of the presentinvention has the following additional advantages.

First, since the p⁺ silicon diffusion layers 5, 7 are anodized after thelayers 5, 7 are formed on the determined areas in advance, the depth andshape of the anodization is more uniform compared to the method in whichthe upper surface of the substrate 2 is directly anodized. Second, sincethe alkali etching is performed after the passivation process iscompleted, the wiring patterns 9 and the bonding pads are notcontaminated by the etchant. Third, since the porous silicon layer 16 isdissolved and removed, the manufacturing process is not limited by theflat orientation of the substrate 2. Fourth, since the manufacturingmethod is basically similar to the process of manufacturing bipolar ICs,the acceleration sensor 1 can be integrated with a bipolar IC.

The present invention is not limited to the above embodiment and can bevaried as follows.

As shown in FIG. 8, the depth of a p⁺ silicon diffusion layer 31 may bechanged to reach the substrate 2. If the anodization is performed inthis state, a current flows along the route shown in FIG. 8, andporosity formation advances in a direction opposite to the current flow.

In the above embodiment, the anodization may be performed without the p⁺silicon diffusion layer 22. Further, in manufacturing the accelerationsensor 1, an n-type polycrystal silicon layer or amorphous silicon layermay be formed instead of the n-type single crystal silicon epitaxialgrowth layer.

In the above embodiment, a bipolar IC, which serves as a signal logiccircuit, may be formed in a space around the mass portion 17 on theupper surface of the substrate 2.

The anodization method of the present invention may be applied tosensors other than the acceleration sensor 1 and further, may be appliedto semiconductor products other than sensors.

The definition of the anodization in the present specification is that acurrent is applied to a substrate as an anode in an electrolyticsolution to form a porous layer in the substrate.

What is claimed is:
 1. A method for anodizing a silicon substratecomprising: providing a p-type single crystal silicon substrate; formingan n-type silicon embedded layer made of n-type silicon on apredetermined area of a first surface of the p-type single crystalsilicon layer, wherein an opening for permitting a current to flow isformed in the center of the n-type silicon embedded layer; forming ann-type silicon layer on the first surface of the p-type single crystalsilicon substrate and on the n-type silicon embedded layer; forming asilicon diffusion layer containing a high-concentration p-type impurityon a predetermined area of the n-type silicon layer, wherein the silicondiffusion layer contacts the n-type silicon embedded layer in thevicinity of the interface between the p-type single crystal siliconsubstrate and the n-type silicon embedded layer, and wherein a gap isdefined between the first surface of the p-type silicon substrate andthe silicon diffusion layer; forming an electrode layer on a secondsurface, which is on the opposite side of the p-type silicon substratefrom the first surface; connecting the anode of a DC power source to theelectrode layer and connecting the cathode to a counter electrode, whichis opposed to the p-type silicon substrate; and concentrating a currentflow to an area corresponding to the opening of the n-type silicon layerin a direction from the second surface of the p-type single crystalsilicon substrate toward the first surface, and advancing porosityformation in the area from the first surface toward the second surface.2. The method according to claim 1 further including forming aninsulation layer having a connection opening on the second surface ofthe p-type single crystal silicon substrate to correspond to the openingof the n-type silicon layer; and the formation of the electrode layerincludes electrically connecting the electrode layer to the p-typesingle crystal silicon substrate through the connection opening.
 3. Themethod according to claim 2 further including forming a silicondiffusion layer containing high-concentration p-type impurity in an areaof the p-type single crystal silicon substrate to correspond to theconnection opening after the formation of the insulation layer.
 4. Themethod according to claim 3, wherein the connection opening is smallerthan the opening of the n-type silicon embedded layer.
 5. The methodaccording to claim 1, wherein the formation of n-type silicon layerincludes forming a first epitaxial growth layer made of n-type siliconon the n-type silicon embedded layer and the p-type single crystalsilicon substrate, and forming a second epitaxial growth layer on thefirst epitaxial growth layer.
 6. The method according to claim 1 furtherincluding forming a deformation gauge on the n-type silicon layer. 7.The method according to claim 6 further including: forming an interlayerinsulation layer on the n-type silicon layer such that the silicondiffusion layer is exposed; forming a wiring on the interlayerinsulation layer; and forming a protection film, which covers an areaexcluding the diffusion layer to expose the surface of the silicondiffusion layer.
 8. A method for anodizing a silicon substratecomprising: providing a p-type single crystal, silicon substrate;forming an n-type silicon embedded layer made of n-type silicon on apredetermined area of a first surface of the p-type single crystalsilicon layer, wherein an opening for permitting a current to flow isformed in the center of the n-type silicon embedded layer; forming ann-type silicon layer on the first surface of the p-type single crystalsilicon substrate and on the n-type silicon embedded layer, wherein then-type silicon embedded layer spans the interface between the p-typesilicon substrate and the n-type silicon layer; forming a silicondiffusion layer containing a high-concentration p-type impurity on apredetermined area of the n-type silicon layer, wherein the silicondiffusion layer contacts at least the n-type silicon embedded layer inthe vicinity of the interface between the p-type single crystal siliconsubstrate and the n-type silicon embedded layer; forming an electrodelayer on a second surface, which is on the opposite side of the p-typesilicon substrate from the first surface; connecting the anode of a DCpower source to the electrode layer and connecting the cathode to acounter electrode, which is opposed to the p-type silicon substrate; andconcentrating a current flow to an area corresponding to the opening ofthe n-type silicon layer in a direction from the second surface of thep-type single crystal silicon substrate toward the first surface, andadvancing porosity formation in the area from the first surface towardthe second surface.
 9. The method according to claim 8 further includingforming an insulation layer having a connection opening on the secondsurface of the p-type single crystal silicon substrate to correspond tothe opening of the n-type silicon layer; and the formation of theelectrode layer includes electrically connecting the electrode layer tothe p-type single crystal silicon substrate through the connectionopening.
 10. The method according to claim 9 further including forming asilicon diffusion layer containing high-concentration p-type impurity inan area of the p-type single crystal silicon substrate to correspond tothe connection opening after the formation of the insulation layer. 11.The method according to claim 10, wherein the connection opening issmaller than the opening of the n-type silicon embedded layer.
 12. Themethod according to claim 8, wherein the formation of n-type siliconlayer includes forming a first epitaxial growth layer made of n-typesilicon on the n-type silicon embedded layer and the p-type singlecrystal silicon substrate, and forming a second epitaxial growth layeron the first epitaxial growth layer.
 13. The method according to claim8, wherein the formation of the silicon diffusion layer includes formingthe silicon diffusion layer such that the layer contacts the p-typesingle crystal silicon substrate and the n-type silicon embedded layer.14. The method according to claim 8 further including forming adeformation gauge on the n-type silicon layer.
 15. The method accordingto claim 14 further including: forming an interlayer insulation layer onthe n-type silicon layer such that the silicon diffusion layer isexposed; forming a wiring on the interlayer insulation layer; andforming a protection film, which covers an area excluding the diffusionlayer to expose the surface of the silicon diffusion layer.